/*
 * LPCD.h
 *
 *  Created on: Oct 11, 2025
 *      Author: Lenovo
 */

#ifndef FM17660K_LPCD_H_
#define FM17660K_LPCD_H_


//ext reg FM176XX  LPCD//////////
#define JREG_LPCDIRQ                 0x16
#define JREG_LPCD_TEST               0x17
#define JREG_QUADSUM_H               0x18
#define JREG_QUADSUM_M               0x19
#define JREG_QUADSUM_L               0x1A
#define JREG_LPCDDELTA_H             0x1B
#define JREG_LPCDDELTA_L             0x1C
#define JREG_LPCDCURR_H              0x1D
#define JREG_LPCDICURR_L             0x1E
#define JREG_LPCDQCURR_L             0x1F
#define JREG_LPCDLAST_H              0x20
#define JREG_LPCDILAST_L             0x21
#define JREG_LPCDQLAST_L             0x22
#define JREG_SARADCCFG1              0x23
#define JREG_SARADCCFG2              0x24
#define JREG_LPCDTHRESHOLD           0x25
#define JREG_LPCDTXCTRL              0x26
#define JREG_LPCDPWRP                    0x28
#define JREG_LPCDPWRN                    0x29
#define JREG_LPCDSLEEPTIMER      0x2A
#define JREG_LPCDRFTIMER             0x2B
#define JREG_LPCDREQATIMER           0x2C
#define JREG_LPCDGMSEL                   0x2D
#define JREG_LPCDCTRL                    0x2E
#define JREG_LPCDMISSWUP             0x2F


/** \name LPCDTEST Register Contents (EXT/0x17)
*/
/*@{*/
#define BIT_DETECT_ONCE         0x20U
/** \name SARADCCFG1 Register Contents (EXT/0x23)
*/
/*@{*/
#define BIT_SARADC_SEL_RSTN         0x80U
#define BIT_SARADC_CLK_SEL          0x40U
#define BIT_ADC_WAIVE_SEL_MODE_1    0x00U
#define BIT_ADC_WAIVE_SEL_MODE_2    0x10U
#define BIT_ADC_WAIVE_SEL_MODE_3    0x20U
#define BIT_ADC_WAIVE_SEL_MODE_4    0x30U

#define   BIT_ADC_SOC_CFG_4                0x00
#define   BIT_ADC_SOC_CFG_8                0x04
#define   BIT_ADC_SOC_CFG_16               0x08
#define   BIT_ADC_SOC_CFG_24               0x0C
/** \name SARADCCFG2 Register Contens (EXT/0x24)*/

#define   BIT_SARADC_SEL_RSTN1                      0x80
#define   BIT_SARADC_MODE_VCM                       0x40

#define   BIT_LPCD_ADC_CMPRDY_DELAY_0      0x00
#define   BIT_LPCD_ADC_CMPRDY_DELAY_1      0x04
#define   BIT_LPCD_ADC_CMPRDY_DELAY_2      0x08
#define   BIT_LPCD_ADC_CMPRDY_DELAY_3      0x0C

#define   BIT_LPCD_ADC_CKDIG_DELAY_0       0x00
#define   BIT_LPCD_ADC_CKDIG_DELAY_1       0x01
#define   BIT_LPCD_ADC_CKDIG_DELAY_2       0x02
#define   BIT_LPCD_ADC_CKDIG_DELAY_3       0x03

#define   BIT_ADC_SAMPLE_MODE_2            0x00
#define   BIT_ADC_SAMPLE_MODE_4            0x01
#define   BIT_ADC_SAMPLE_MODE_8            0x02
#define   BIT_ADC_SAMPLE_MODE_16           0x03
/** \name LPCDTXCTRL Register Contents (EXT/0x26)
*/
/*@{*/

#define BIT_LPCD_TX_2RF_EN              0x20U
#define BIT_LPCD_TX_1RF_EN          0x10U
#define BIT_LPCD_INVTX2RFON         0x08U
#define BIT_LPCD_INVTX1RFON             0x04U
#define BIT_LPCD_INVTX2RFOFF        0x02U
#define BIT_LPCD_INVTX1RFOFF        0x01U

/** \name LPCDSLEEPTIMER Register Contents (EXT/0x2A)
*/
/*@{*/


/** \name LPCDRFTIMER Register Contents (EXT/0x2B)
*/
/*@{*/
#define BIT_LPCD_TX_PWR_SCALE_18                0x00U
#define BIT_LPCD_TX_PWR_SCALE_14                0x20U
#define BIT_LPCD_TX_PWR_SCALE_12                0x40U
#define BIT_LPCD_TX_PWR_SCALE_34                0x60U
#define BIT_LPCD_TX_PWR_SCALE_1                 0x80U
#define BIT_LPCD_TX_PWR_SCALE_2                 0xA0U
#define BIT_LPCD_TX_PWR_SCALE_3                 0xC0U
#define BIT_LPCD_TX_PWR_SCALE_4                 0xE0U



#define BIT_LPCD_RF_TIMER_5US                   0x00U
#define BIT_LPCD_RF_TIMER_10US                  0x01U
#define BIT_LPCD_RF_TIMER_15US                  0x02U
#define BIT_LPCD_RF_TIMER_20US                  0x03U
#define BIT_LPCD_RF_TIMER_25US                  0x04U
#define BIT_LPCD_RF_TIMER_30US                  0x05U
#define BIT_LPCD_RF_TIMER_35US                  0x06U
#define BIT_LPCD_RF_TIMER_40US                  0x07U
#define BIT_LPCD_RF_TIMER_50US                  0x08U
#define BIT_LPCD_RF_TIMER_60US                  0x09U
#define BIT_LPCD_RF_TIMER_70US                  0x0AU
#define BIT_LPCD_RF_TIMER_80US                  0x0BU
#define BIT_LPCD_RF_TIMER_100US             0x0CU
#define BIT_LPCD_RF_TIMER_120US             0x0DU
#define BIT_LPCD_RF_TIMER_150US             0x0EU
#define BIT_LPCD_RF_TIMER_200US             0x0FU

/** \name LPCDREQATIMER Register Contents (EXT/0x2C)
*/
/*@{*/
#define BIT_LPCD_TXPWR_SCALE_1                      0x80U
#define BIT_LPCD_Reqa_TIMER_80US                    0x00U
#define BIT_LPCD_Reqa_TIMER_100US                   0x01U
#define BIT_LPCD_Reqa_TIMER_120US                   0x02U
#define BIT_LPCD_Reqa_TIMER_150US                   0x03U
#define BIT_LPCD_Reqa_TIMER_200US                   0x04U
#define BIT_LPCD_Reqa_TIMER_250US                   0x05U
#define BIT_LPCD_Reqa_TIMER_300US                   0x06U
#define BIT_LPCD_Reqa_TIMER_400US                   0x07U
#define BIT_LPCD_Reqa_TIMER_500US                   0x08U
#define BIT_LPCD_Reqa_TIMER_600US                   0x09U
#define BIT_LPCD_Reqa_TIMER_800US                   0x0AU
#define BIT_LPCD_Reqa_TIMER_1000US                  0x0BU
#define BIT_LPCD_Reqa_TIMER_1200US                  0x0CU
#define BIT_LPCD_Reqa_TIMER_1600US                  0x0DU
#define BIT_LPCD_Reqa_TIMER_2000US                  0x0EU
#define BIT_LPCD_Reqa_TIMER_2500US                  0x0FU
#define BIT_LPCD_Reqa_TIMER_3000US                  0x10U
#define BIT_LPCD_Reqa_TIMER_3500US                  0x11U
#define BIT_LPCD_Reqa_TIMER_4000US                  0x12U
#define BIT_LPCD_Reqa_TIMER_5000US                  0x13U
#define BIT_LPCD_Reqa_TIMER_7000US                  0x14U
/** \name LPCDGMSEL Register Contents (EXT/0x2D)*/
#define   BIT_LPCD_ENB_AGC                            0x04U
#define   BIT_LPCD_GM_SEL_0                0x00
#define   BIT_LPCD_GM_SEL_1                0x01
#define   BIT_LPCD_GM_SEL_2                0x02
#define   BIT_LPCD_GM_SEL_3                0x03
#define   BIT_SEL_TX_DRV_FB                0x10
#define   BIT_RF_DET_EN                      0x20
/** \name LPCDCTRL Register Contents (EXT/0x2E)*/
#define  BIT_LPCD_IRQINV                  0x80U
#define  BIT_LPCD_IRQPUSHPULL             0x40U
#define  BIT_LPCD_DISABLE                 0x00
#define  BIT_LPCD_SIGOUTMODE1_ENABLE      0x01
#define  BIT_LPCD_INTERNALMODE1_ENABLE    0x02
#define  BIT_LPCD_SIGOUTMODE2_ENABLE      0x05
#define  BIT_LPCD_INTERNALMODE2_ENABLE    0x06

#define   LPCD_RX_CHANGE_MODE               0x00
#define   LPCD_REQA_MODE                    0x08
#define   LPCD_COMBINE_MODE                 0x10

/** \name LPCDCTRL Register Contents (EXT/0x2F)*/
#define  BIT_LPCD_RXCHANGE_JUDGE_MODE       0x80U
/** \name CM_ANACFG Register Contents (EXT/0x5f)*/
#define  BIT_LPCD_SLEEP_EN                  0x80U
#define  BIT_LPCD_ENB_DISCG15               0x40U
#define  BIT_LPCD_BG_TRIM_11                0x18U

#define LPCD_THRSH      0x01
#define LPCD_CWP            0x08
#define LPCD_CWN            0x08


extern unsigned char Lpcd_Init(void);
extern void Enter_HPD(void);
extern void Exit_HPD(void);
extern void Lpcd_Get_ADC_Value(void);

#endif /* FM17660K_LPCD_H_ */
